2023 Memory Access Impact on Performance Assume that main memory accesses take 80 ns | Assignment Collections
Computer Science 2023 Computer Architecture
2023 Memory Access Impact on Performance Assume that main memory accesses take 80 ns | Assignment Collections
Memory Access Impact on Performance:
Assume that main memory accesses take 80 ns and that memory accesses are 42% of all instructions. The L1 cache has a miss rate of 9% and a hit time of 0.58 ns.
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1.Assume that the L1 hit time determines the cycle time for the processor. What is the clock rate? |
1._______ |
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2.What is the Average Memory Access Time for the processor? |
2.________ |
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3.Assuming a base CPI of 1.0 without any memory stalls (once the pipeline is loaded), what is the total average CPI for the processor? |
3. _______ |
We will consider the addition of an L2 cache to try to reduce the average CPI; on a miss, P1 will now first check L2 cache, and only if that is a miss, will then need a main memory access. The L2 miss rate is 85%, and L2 hit time is 4.88ns
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4.What is the AMAT for the processor, with the inclusion of the L2 cache? |
4._________ |
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5. Assuming a base CPI of 1.0 without any memory stalls, and using the same instruction miss as part 1 of this question, what is the total CPI (for all instruction types) for P1 with the addition of an L2 cache? |
5._________ |
Question #1: The cache for this problem has 16 words. You are going to evaluate the cache performance based on different mapping schemes, and different size blocks, to try to come up with the best mapping and block arrangement for this series of memory access calls.
Your mappings will be:
16 one-word blocks, Direct Mapping
16 one-word blocks, Fully Associative Mapping
4 4-word blocks, Direct Mapping
4 4-word blocks, Fully Associative Mapping
4-way Set-Associative, 16 one-word blocks
For each of the schemes,
1. Fill out the “top” table of “tags”
2. Show the placement of the block in the “bottom” table
3. Count the “hits” and “misses”
4. Compare the hit/miss ratios for the different mappings and block arrangements
If you were designing the cache, what do you think would have to most impact on the performance: larger block sizes, or different mapping schemes? Explain your reasoning.
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Word Address |
Word Bit Address |
Direct 16 |
Direct 4 |
Fully Assoc. 16 Tag |
Fully Assoc. 4 |
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2 |
00000010 |
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3 |
00000011 |
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11 |
00001011 |
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16 |
00010000 |
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21 |
00010101 |
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13 |
00001101 |
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64 |
01000000 |
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48 |
00110000 |
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19 |
00010011 |
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11 |
00001011 |
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3 |
00000011 |
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22 |
00010110 |
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4 |
00000100 |
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27 |
00011011 |
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6 |
00000110 |
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11 |
00001011 |
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# hits : # misses _________ ________ _________ _________
CAT size in bits:
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16 Blocks |
Direct Map |
Associative |
4 Blocks |
Direct Map |
Associative |
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0 (0000) |
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0 (00) |
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1 (0001) |
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2 (0010) |
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3 (0011) |
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4 (0100) |
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1 (01) |
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5 (0101) |
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6 (0110) |
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7 (0111) |
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8 (1000) |
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2 (10) |
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9 (1001) |
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10 (1010) |
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11 (1011) |
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12 (1100) |
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3 (11) |
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13 (1101) |
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14 (1110) |
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15 (1111) |
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4-way Set Associative with 1-word blocks
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Word Address |
Word Bit Address |
4 way set |
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2 |
00000010 |
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3 |
00000011 |
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11 |
00001011 |
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16 |
00010000 |
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21 |
00010101 |
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13 |
00001101 |
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64 |
01000000 |
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48 |
00110000 |
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19 |
00010011 |
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11 |
00001011 |
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3 |
00000011 |
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22 |
00010110 |
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4 |
00000100 |
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27 |
00011011 |
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6 |
00000110 |
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11 |
00001011 |
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# hits : # misses ____________
CAT size in bits: ____________
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4 way sets |
Slot 1 |
Slot 2 |
Slot 3 |
Slot 4 |
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0 (00) |
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1 (01) |
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2 (10) |
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3 (11) |
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